Gate delays

As an example of the level of sophistication of Logisim's algorithm, consider the following circuit, which I've named Const0.

This "obviously" always outputs 0. But NOT gates don't react instantaneously to their inputs in reality, and neither do they in Logisim. As a result, when this circuit's input changes from 0 to 1, the AND gate will briefly see two 1 inputs, and it will emit a 1 briefly. You won't see it on the screen. But the effect is observable when we use this as a subcircuit.

Poking the 0 input now will lead to an instantaneous 1 going into the D flip-flop, and so the flip-flop's value will change to 1.

More sophisticated components built into Logisim have larger gate delays, although the values for these gate delays is somewhat arbitrary and may not reflect reality.

From a technical point of view, it is relatively easy to deal with this level of sophistication in a single circuit. Dealing with gate delays across subcircuits, though, is significantly more complex, and very few educational packages handle it correctly (including Logisim prior to version 2.0).

Note that I'm stopping short of saying that Logisim always handles it correctly. But at least it tries.

Next: Oscillation errors.