Logisim's propagation algorithm is more than sophisticated enough
for almost all educational purposes; but it is not sophisticated
enough for industrial circuit design. In order from most damning to
least damning, the shortcomings of Logisim's propagation technique
include:
Except for the issue of gate delays, Logisim does not particularly
concern itself with timing issues. It is very idealized, so that a pair of NOR
gates in an S-R latch configuration will toggle in lockstep infinitely, rather
than the circuit eventually settle into a stable state.
Logisim cannot simulate subcircuits whose pins sometimes behave
as inputs and sometimes behave as outputs. Components built using
Java can have such pins, though: Within the built-in libraries,
the Memory library's RAM circuit contains a D pin that can act both
as an input and as an output.
Logisim cuts off its simulation after a fixed number of iterations
assuming that there is an oscillation error.
Conceivably, a large circuit that does not oscillate could lead to
trouble.
Logisim does nothing with respect to discriminating between
voltage levels: A bit can be only on, off, unspecified, or error.
There are additional shortcomings, too, that I have omitted because
they are so obscure that if you were aware of them, it would be obvious
that Logisim comes nowhere close to that level. As an extreme example,
I have a friend who works for a major chip manufacturer, and his
job is to worry about "bubbles" in chips' nanometer-wide wires growing
and leading to random disconnection.
Even beyond this, I am not a circuit design specialist; thus,
there may well be errors in the propagation technique of which I am
not aware. I welcome corrections from experts.